The lab materials heavily follow the design from Prof. Xiaohong Jiang, who provides generous help to develop other course materials as well.
| 1. | Learn the operation of Spartan3E Board and the usage of ISE. |
| 2. | Understand the principle of the pipelined CPU and MIPS instructions. |
| 3. | Design the pipelined CPU that can execute 31 MIPS instructions correctly on Spartan3E board step by step according to the project tutorial. |
| Introduction | |
| Lab 1 |
Review & warmup the experiment environment of the course Computer Organization: Spartan 3E board, ISE environment; Try to update verilog code of the display part of multi-cycle CPU to make it run correctly on 3E board; Try to add one new branch instruction. |
| Lab 2 | Implement 5-stage pipelined CPU with 15 MIPS instructions. |
| Lab 3 | Implement "stall" that makes CPU correctly execute instructions against pipelining hazards. |
| Lab 4 | Implement “forwarding paths” toward faster CPU. |
| Lab 5 |
Implement a pipelined CPU with 31 MIPS instructions; Use predict-not-taken policy to solve control hazard. |
| Lab 6 |
Cache implementation (tentative) |
| 2% | Participation & performance |
| 5% | Each of Lab 1 to Lab 6 (tentative) |
Notes: A demo of the experiment result is required during the lab session; a report should be submitted per instructions.
| Demo | Report | |
| Lab 1 | 2018.10.22 | 2018.10.29 |
| Lab 2 | 2018.11.26 | 2018.12.03 |
| Lab 3 | 2018.12.17 | 2019.01.07 |
| Lab 4 | 2018.12.24 | 2019.01.07 |
| Lab 5 | 2019.01.07 | 2019.01.14 |
TBD