Introduction to Computer Architecture

College of Computer Science and Technology, Zhejiang University, Spring 2016
Thursday 13:15/14:05 - 17:30, No. 4 Teaching Building
Room 411 Lecture, Room 301 Lab

Acknowledgement

The lab materials heavily follow the design from Prof. Xiaohong Jiang, who provides generous help to develop other course materials as well.

Lab Objective

1.	Learn the operation of Spartan3E Board and the usage of ISE.
2.	Understand the principle of the pipelined CPU and MIPS instructions.
3.	Design the pipelined CPU that can execute 31 MIPS instructions correctly on Spartan3E board step by step according to the project tutorial.

Lab Sessions

	Introduction
Lab 1	Review & warmup the experiment environment of the course Computer Organization: Spartan 3E board, ISE environment; Try to update verilog code of the display part of multi-cycle CPU to make it run correctly on 3E board; Try to add one new branch instruction.
Lab 2	Implement 5-stage pipelined CPU with 15 MIPS instructions.
Lab 3	Implement "stall" that makes CPU correctly execute instructions against pipelining hazards.
Lab 4	Implement “forwarding paths” toward faster CPU.
Lab 5	Implement a pipelined CPU with 31 MIPS instructions; Use predict-not-taken policy to solve control hazard.
Lab 6	Cache implementation - TBD

Grading: 32%

2%	Participation & performance
5%	Each of Lab 1 to Lab 6

Notes: A demo of the experiment result is required during the lab session; a report should be submitted per instructions.

Report

Report template
Report Submission Website: http://10.78.18.200:8080/Platform/ intranet only, register with zju email address

Lab Opening Hours

TBD