| Kai Bu | Email: kaibu@zju.edu.cn |
| Office: Room 503 Zetong Building | Office Hour: by appointment |
This course systematically introduces the fundamentals of computer architecture from the perspective of the whole computer system. The main content of this course consists of fundamentals of computer design, instruction set principles, pipelining implementation, memory hierarchy design, and multiprocessors. Students are also expected to practice and master hardware design toolkits through lab sessions. The course objective is that students not only understand the fundamental concepts but also implement a pipelined CPU supporting 31 MIPS instructions in Xilinx ISE environment using Verilog and verify its correctness on FPGA boards.
Computer Architecture: A Quantitative Approach, Fifth Edition, John L. Hennessy and David A. Patterson. Morgan Kaufmann, 2011.
Computer Organization, Assemble Language, Operating System
| 4% | Class participation & performance |
| 16% | Homework |
| 8% | Pop quiz |
| 32% | Lab assignments |
| 40% | Final exam |
| Bonus 5% | Research Warm-up! |
| Bonus 5% | Active class participation via thoughtful questions or answers with bonus 1% per time |