The lab materials heavily follow the design from Dr. Zonghui Wang, who provides generous help to develop sample code as well.
| 1. | Learn the operation of the SWORD board and the usage of Xilinx Vivado. |
| 2. | Understand the principle of the pipelined CPU and RISC-V instructions. |
| 3. | Design the pipelined CPU that can execute RV32I instructions correctly on the SWORD board step by step according to the lab tutorial. |
| 4. | Enhance the pipelined CPU with various caching and scheduling techniques. |
| Lab 01 |
Review & warmup the experiment environment of the course of Computer Organization: SWORD board, Xilinx Vivado environment; Implement a 5-stage pipelined CPU with forwarding and predicted-not-taken to support RV32I instructions. |
| Lab 02 | Implement handling of interrupt and exception on the pipelined CPU from Lab 01. |
| Lab 03 | Implement a two-way associative cache through simulation. |
| Lab 04 | Incorporate the two-way associative cache from Lab 03 to the pipelined CPU from Lab 02. |
| Lab 05 | Extend the pipelined CPU from Lab 02 to support multi-cycle operations, out-of-order execution, and hazard detection. |
| Lab 06 |
Extend the pipelined CPU from Lab 05 to support dynamic scheduling such as Scoreboarding or Tomasulo. |
| Lab 01 | Lab 02 | Lab 03 | Lab 04 | Lab 05 | Lab 06 |
| 6% | 4% | 3% | 4% | 7% | 8% |
Notes: A demo of the experiment result is required during the lab session; a report should be submitted per instructions.
| Demo | Report | |
| Lab 01 | 2024.09.30 | 2024.10.12 |
| Lab 02 | 2024.10.14 | 2024.10.21 |
| Lab 03 | 2024.10.28 | 2024.11.04 |
| Lab 04 | 2024.11.04 | 2024.11.11 |
| Lab 05 | 2024.11.25 | 2024.12.02 |
| Lab 06 | 2024.12.23 | 2024.12.30 |
TBD