| Kai Bu | Email: kaibu@zju.edu.cn |
| Office: Room 503 Zetong Building | Office Hour: by appointment |
| Yunjie Chu | Email: yj_chu@zju.edu.cn |
| Chengke Zhang | Email: zhangchengke@zju.edu.cn |
| Office: Room 503 Zetong Building | Office Hour: by appointment |
This course systematically introduces the fundamentals of computer architecture from the perspective of the whole computer system. The main content of this course consists of fundamentals of computer design, instruction set principles, pipelining implementation, memory hierarchy design, and exploitation of parallelism at instruction-, data-, and thread-level. Students are also expected to practice and master hardware design toolkits through lab sessions. The course objective is that students not only understand the fundamental concepts but also implement a pipelined CPU supporting RISC-V instructions in Xilinx Vivado environment using Verilog and verify its correctness on FPGA boards.
Computer Architecture: A Quantitative Approach, Sixth Edition, John L. Hennessy and David A. Patterson. Morgan Kaufmann, 2017.
Computer Organization, Digital Logic, Assembly Language
| 4% | Class participation & performance |
| 16% | Assignment |
| 32% | Lab OR Research |
| 8% | Quiz |
| 40% | Final exam: 08:00 - 10:00, January 02, 2025. |